Strained and used in channel. This is achieved by

Strained silicon is a layer of
silicon whose atoms interatomic distance is stretched beyond their original
distance and used in channel. This is achieved by superimposing the silicon
layer on Silicon Germanium (SiGe) substrate. Fig 2 shows the normal silicon vs
strained silicon over SiGe. The silicon atoms get aligned with the underlying
SiGe atoms, which are place little farther apart when compared to Si. This
stretched strained silicon atoms interatomic space is increased and hence the
interatomic force reduces thereby increasing the easy movement of electrons.

This increases the mobility of electrons resulting in better chip performance
and lower power consumption 2. These electrons can move 70% faster allowing strained
silicon to switch 35% faster 24.

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technique has become an integral part of the International Technology Roadmap
for Semiconductors (ITRS), starting at 90nm technology node 24. Strained
silicon was implemented in Intel’s 90nm technology in 2003 11. There are two
basic approaches to introduce strain into transistor channel: global and local

strain is the type where the stress is induced in the channel of the MOSFET.

This is done by epitaxially growing a SiGe buffer layer above the silicon
substrate as shown in Fig. 3. Now, silicon is grown above the SiGe layer whose
crystalline lattice is slightly larger than the crystalline lattice structure
of silicon. Silicon grown above the SiGe layer is stretched which induces
biaxial strain to provide increased spacing between Si atoms 4% more than
normal Si atoms. The strain produced causes change in the energy bands for both
electrons and holes. This results in increased mobility of the carriers and increases
the drive current to provide improved performance 25.   

strain is introduced by replacing the conventional silicon source and drain
with SiGe source and drain as shown in Fig. 4. This is achieved by etching the
silicon from the source and drain regions selectively and growing SiGe
epitaxially over it. As said earlier than SiGe cystal lattice is slightly
larger than Si, the channel region between SiGe source and drain experiences
uniaxial compressive stress. This uniaxial compressive stress enhances the
mobility of holes and thus results in improved performance of 65% drain current
in PMOS 25. This type of strain is a real boost for PMOS since their
performance is always on the lower side when compared to NMOS. Therefore, this
local strain very advantageous for PMOS.