Abstract – In

this paper, a new single – phase Alternating Current – Direct Current Power

factor correction bridgeless rectifier with multiplier stage to improve the

efficiency at low input voltage and reduce the switch – voltage stress is

introduced. The absence of an input rectifier bridge in the proposed rectifier

and the presence of only two semiconductor switches in the current flowing path

during each switching cycle result in less conduction losses and improved

thermal management. Lower switch voltage stress allows utilizing a MOSFET with

lower RDS – on. The proposed topology is designed to operate in

discontinuous conduction mode (DCM) to achieve almost a unity power factor and

low total harmonic distortion (THD) of the input current. The DCM operation

gives additional advantages such as zero – current turn – on in the power

switches and simple control circuitry. Simulation result for 200W / 420 Vdc at

universal line voltage range to evaluate the performance of the proposed

bridgeless PFC rectifier are detailed.

Index

Terms – Bridgeless rectifier, Discontinuous conduction mode, Single ended primary

inductor converter

I INTRODUCTION

Bridgeless

PFC modified SEPIC rectifier fed supply from AC source like electricity board

power. Single Ended Primary Inductor Converter is combination of rectifier and

converter. SEPIC rectifier is having several advantages such as: step up and

step down capability in addition to magnetic coupling that will lead to

reduction in input current ripple. Controller

circuit of the driver and PIC microcontroller are fed power from power supply.

Fig 1

Block diagram of bridgeless PFC modified SEPIC rectifier diagram

Mr. M.Purushothaman Assistant

Professor,

T he output of the modular SEPIC

converter power supply is fed to the load.

II

EXISTING SYSTEM

The DCM

operation requires a high qulity boost inductor since it must switch extremely

high peak ripple current and voltage. As a result, a more robust input filter

must be employed to suppress the high frequency components of the pulsating input

current, which increase the overall weight and cost of the rectifier. In

addition, several PFC topologies have an inverting output.

Fig 2 modified

SEPIC Rectifier

Modified SEPIC

rectifier of the existing system is having more number of disadvantages like

complex circuit, bridge rectifier circuit is used, conduction losses is high

and switch voltage stress is high

111

PROPOSED SYSTEM

In this paper, a

new single phase PFC bridgeless rectifier is operated in discontinuous conduction

mode. The DCM operation results in soft turn – on switching and relatively low

inrush current. The voltage gain can be extended without extreme duty cycle.

The proposed bridgeless rectifier is coupled magnetic configurations, results

in higher overall efficiency and higher power density. The bridgeless

configuration will reduce the conduction losses and the multiplier cell (D1,

C3) and (D2 , C3) will increase the gain and

reduce the switch voltage stress. The proposed circuit consist of two MOSFET

switches (Q1, Q2) and two slow diodes (Dp , Dn).

Fig 3 bridgeless

modified SEPIC rectifier

The advantages

of the proposed system having simple circuitry, lower voltage stress in whole

operation, conduction losses is reduced and higher efficiency.

IV

MODE OF OPERATION

Bridgeless SEPIC

PFC rectifier is having two switches Q1, Q2 and two

diodes are serisesly connected with inductor in every half cycle of the

operation. To shown in the positive and negative half line periods equivalent

circuit diagram.

Fig 4(a) During

positive half- line period. (b) During

negative half – line period.

Positive

Half –line Mode of Operation

Since the

proposed circuit consist of two symmetrical configurations as illustrated in

fig.4,the circuit is analyzed for the positive half line cycle configuration

shown in

fig.4a

Assuming that

the three inductors are operating in DCM, then the circuit operation during one

switching period Ts in a positive half – line period can be divided

into three distinct operating modes as shown in fig 5 (a) – (c), and it can be

described as follows.

Fig5 (a) switch

ON topology. (b) Switch OFF topology. (c) DCM topology.

No

of stages

Switches

Diodes

Inductor

current

First

stage

Q1,

Ton

D1

, D0 is reverse biased

diLn/dt

= Vac/Ln

Second

stage

Q2,

Toff

D1

, D0 is forward biased

diLn/dt

= -Lc/Ln

Third

stage

Q2,

Toff

D1,

D2 reverse biased

constant

A. First Stage

In this stage, switch Q1 is turned-on by

the control signal and both diodesD1 and Do are

reversed biased as shown in Fig. 4(a).

In this stage, the three-inductor currents increase linearly at a rate

proportional to the input voltage vac

diLn/dt = vac/Ln, n= 1, 2, o. (1)

B. Second Stage

During this subinterval, switch Q1 is turned-off

and both diodes D1 and Do will conduct simultaneously providing a path for the three

inductors’ currents as shown in Fig. 4(b). In this stage, the three inductors’

currents decrease linearly at a

rate proportional to the capacitor C1 voltage VC1 . This stage ends when the sum of the currents flowing in the inductors

addsup to zero, hence diodes D1 and Do are

reverse biased

diLn/dt= ?vC1/Ln, n= 1, 2, o. (2)

C. Third Stage

In this stage, switch Q1 remains

turned-off while both diodesD1 and Do are

reverse biased as illustrated in Fig. 4(c). Diode Dp provides a path for

iLo. The three inductors behave as current sources, which keeps the

currents constant. Hence, the voltage across the three inductors is zero. This

period ends when switchQ1 is turned-on initiating the next turn-on of the switching cycle. Fig. 5

illustrates the theoretical DCM waveforms during one switching period Ts for

the proposed rectifier.

DESIGN PROCEDURE

A simplified design procedure is presented in this section to

determine the component values of the proposed rectifier for the

following power stage specifications.

1) input voltage: 120 V at 50 Hz;

2) output voltage: 400 V;

3) output power: 200 W;

4) switching frequency fs = 50 kHz;

5) maximum input current ripple?iL1 = 10%of fundamental input current;

6) output voltage ripple ?vo = 2% of Vo .

From the

aforementioned data and assuming that the efficiency is 100%, the

values of the circuit components are calculated based on the following

procedure:

1) find Kcrit from (15);

2) find Le from (8) for a given K